Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{188756,
        author = {Lavanya K and Lavanya M and Muktha M and Mythili L and Prathima A},
        title = {ASIC implementation of 8-Bit vedic multiplier using Cadence},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {7},
        pages = {3256-3261},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=188756},
        abstract = {This paper presents the design and ASIC implementation of an 8-bit Vedic multiplier using the Urdhva Tiryagbhyam sutra in 90 nm CMOS technology. A hierarchical structure built from 2×2 and 4×4 Vedic blocks forms the complete 8×8 architecture. The ASIC flow covers RTL modelling, simulation, synthesis, physical design, and parasitic extraction. The study highlights how Vedic mathematics enables parallel partial-product generation and modular, low-complexity design suitable for DSP, embedded systems, and low-power VLSI applications.},
        keywords = {Vedic Multiplier, ASIC Design, Urdhva Tiryagbhyam, CMOS Technology, Physical Design, Cadence Innovus.},
        month = {December},
        }