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@article{190073,
        author = {kasuba ramakrishna jithendra and Dr G Ramana Murthy},
        title = {Placement of logic cells and Power impact with Clock Cell placement},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {8},
        pages = {7389-7392},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=190073},
        abstract = {Power optimization is a big challenge in the IC industry. Generally power dissipation come into two categories. One is Static power and other is Dynamic power. Here we focus more on Dynamic power dissipation, which is more dependent on clock network. Clocks do switch more frequently and drive much larger capacitances. Clock networks consume up to 40% of the total power. With register clustering we can reduce clock power. Placing registers in the same leaf cluster of the clock trees in a smaller area. With this, leaf-level wire capacitance of the clock tree is reduced. Finally, ‘Net Switching Power’ is reduced.},
        keywords = {placement, clock tree synthesis, clock cell clustering, routing},
        month = {January},
        }