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@article{192563,
        author = {K.VINAY PRASAD and L.DAMODAR REDDY and K.SAI ROHIT KUMAR},
        title = {DESIGN OF LOW-POWER 7T SRAM WITH 45NM CMOS TECHNOLOGY},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {9},
        pages = {1877-1881},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=192563},
        abstract = {An extremely small 7-transistor (7T) SRAM cell has been developed using the 45 nm CMOS technology which lowers the amount of energy consumed by a typical 6T SRAM design and increases its reliability and performance. In addition to a new write circuitry the 7T SRAM was optimized in terms of transistor size to provide a reduction of up to 40-50% in power usage per operation compared to standard 6T SRAM designs. Simulations performed by Cadence also demonstrated that this circuit is highly resistant to process variation and reliable. This architecture can be used in low voltage VLSI applications today and will support all types of SRAM array architectures including word line decoders, sensing amplifiers and transmission gates.},
        keywords = {Cadence simulation, 7T SRAM, Low-power design, CMOS technology, VLSI design.},
        month = {February},
        }