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@article{194202,
        author = {PORIKA SINDHUPRIYA and MALOTHU JAGAN and MANCHIRALA SANTHOSH and PAPINENI VISHNUSAI and DR.RADHAMMA},
        title = {Design and Implementation Of Anti-Glitch Multiplexer Using Verilog HDL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {10},
        pages = {2911-2915},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=194202},
        abstract = {Glitch-induced power dissipation and signal instability remain critical challenges in high-speed digital systems and asynchronous circuit design. Traditional multiplexers are prone to transient pulses, or glitches, which occur due to unequal propagation delays across different input paths during select line transitions. This paper presents the Design and Implementation of an Anti-Glitch Multiplexer using Verilog HDL, specifically engineered to eliminate these hazardous transitions.
The proposed architecture incorporates redundant logic and specialized timing constraints to ensure a "make-before-break" transition, providing a stable output even when select signals are non-ideal. By utilizing a glitch-aware logic synthesis approach, the design effectively masks intermediate states that typically trigger unwanted toggling. The implementation is verified through extensive simulation using industry-standard EDA tools, where the performance is benchmarked against conventional multiplexer designs.
Results demonstrate a significant reduction in dynamic power consumption and a marked improvement in the Signal-to-Noise Ratio (SNR) of the data path. The design is highly scalable and synthesized for FPGA/CPLD targets, making it an ideal component for clock switching units, power-sensitive IoT devices, and robust communication interfaces.},
        keywords = {Anti-Glitch, Multiplexer, Verilog HDL, Logic Hazards, Digital Design, Low Power, VLSI.},
        month = {March},
        }