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@article{198411,
        author = {R.SOWMYA and M.SHAILI and M.JASWANTH and M.HARISH and MRS.N.VISRANTHAMMA},
        title = {DESIGN AND ANALYSIS OF HYBRID 10T ADDER USING POWER GATING TECHNIQUE FOR LOW POWER APPLICATION},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {8580-8584},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198411},
        abstract = {In the era of portable electronics and high-performance computing, the demand for ultra-low power consumption in VLSI circuits has become a primary design constraint. As the fundamental building block of digital signal processing (DSP) and microprocessor architectures, the performance of the Full Adder significantly influences the overall efficiency of complex systems. This project proposes the design and analysis of a hybrid 10-transistor (10T) Full Adder optimized for low-power applications using the Power Gating technique.
The proposed hybrid architecture strategically combines transmission gate logic and static CMOS logic styles to achieve a balance between reduced transistor count and full-swing output voltage. To further mitigate leakage power during standby mode a critical concern in deep sub-micron technologies a power gating mechanism (MTCMOS) is integrated. This technique utilizes high-threshold sleep transistors to disconnect the circuit from the power supply during inactive periods, effectively suppressing sub-threshold leakage currents.
Performance evaluation is conducted through extensive simulations using industry-standard tools (e.g., Cadence Virtuoso or Mentor Graphics) at various technology nodes. 
Simulation results demonstrate that the proposed hybrid 10T adder with power gating significantly reduces total power consumption and improves PDP compared to traditional designs. This makes the proposed architecture highly suitable for IoT devices, wearable sensors, and battery-operated VLSI systems where energy efficiency is paramount.},
        keywords = {VLSI, Hybrid Full Adder, 10T Adder, Power Gating, MTCMOS, Low Power Design, Leakage Reduction, Power-Delay Product (PDP).},
        month = {April},
        }