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@article{194458,
        author = {Adusumilli Bhumika and Dwarapudi Ravi Kumar and Edara Lakshmi Thineetha and Bitra Jyothi and Abdul Kalam and Prof. D. Murali},
        title = {Energy - Efficient Jitter Reduction Using Digital Filters And Advanced Smart Clock Sources},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {10},
        pages = {3954-3959},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=194458},
        abstract = {This project focuses on energy- efficient jitter control in VLSI and digital clock circuits by using digital filters and smart clock sources. The main goal is to reduce unwanted timing variations (jitter) in high-speed signals, which can lead to errors and lower system reliability. Digital filters, such as FIR filters, are applied to clean the clock signal by removing noise and disturbances. Smart clock sources like phase-locked loops (PLL) and adaptive clock circuits dynamically adjust timing, ensuring stable signal transmission and reduced power consumption. By combining these methods in FPGA hardware, the system achieves better signal integrity, more accurate timing, and lower power usage. The approach is especially important in modern electronics, where efficient and reliable data transfer is critical. This project explores the practical implementation, performance improvements, and power savings achieved through integrated digital filtering and adaptive clock control.},
        keywords = {Energy efficient, jitter control, digital filter, smart clock source, FPGA, VLSI, phase-locked loop, signal integrity, power saving.},
        month = {March},
        }