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@article{194993,
        author = {Yogita Neknarayan Dubey and Kashish Rohidas Janole and Shruti Dipak Bijwe and Tejaswini Manoj Khandre and Sakshi Vijay Rathod and Dr. Nilesh N. Kasat},
        title = {VHDL Based Firewall Implementation Using XC9572 CPLD},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {10},
        pages = {5900-5905},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=194993},
        abstract = {This project designs a high-speed hardware firewall using VHDL on a CPLD (Xilinx XC9572). Unlike software firewalls that can slow down due to heavy network traffic, this hardware firewall filters data directly at the logic gate level, enabling Realtime and low-latency security. The system continuously scans 8-bit incoming data patterns and checks for a malicious pattern ‘10101010’. If this pattern is detected, the data is blocked and a red LED turns on. If the data is safe, it is allowed to pass and a green LED turns on. The design was created using Xilinx ISE Design Suite and programmed onto the CPLD using the JTAG interface. The results show that CPLDs can be used as fast and reliable embedded hardware security filters.},
        keywords = {CPLD, Embedded Systems Security, Hardware Firewall, Network Security, VHDL, Xilinx XC9572},
        month = {March},
        }