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@article{198632,
        author = {Varad Nangare and Riya Bhogan and Pushkar Bagal and Akhil Masurkar},
        title = {Enhanced Gain and Power Efficiency in CMOS Amplifiers for DAC Applications Using Cascode Current Mirror in 180nm Technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {9144-9149},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198632},
        abstract = {This paper presents the design of low-power, high-gain CMOS amplifiers in 180nm technology using Cadence Virtuoso for Digital to Analog Converter (DAC) interface applications. Various topologies, including common-source stages, cascode structures, and two-stage operational amplifiers, are analyzed. A cascode current mirror is introduced to replace the conventional active load, improving output impedance and voltage gain with minimal power increase. The proposed two-stage operational amplifier achieves a gain of 61.42 dB while consuming 72.61 µW at a 1.8 V supply. Compared to a 130nm baseline design, the proposed implementation offers up to 17 dB higher gain and approximately 89% lower power consumption, making it suitable for DAC and mixed-signal applications.},
        keywords = {Common source amplifier, differential amplifier, operational amplifier, resistive load, active load, current mirror, gain, power dissipation},
        month = {April},
        }