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@article{198660,
        author = {G.V.SUBBA RAO and MUDA NITHIN KUMAR and N.SHREVAN KUMAR and M.ADARSH GOUD and N.LOKESH},
        title = {DESIGN AND SIMULATION OF HIGH SPEED AND LOW POWER ANALOG TO DIGITAL CONVERTER},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {11},
        pages = {9552-9556},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=198660},
        abstract = {This paper presents the design and simulation of a high-speed, low-power Successive Approximation Reg-ister (SAR) Analog-to-Digital Converter (ADC) using RTL modelling. The SAR architecture is chosen for its efficient conversion mechanism and reduced hardware complexity. To support high-speed data transfer, a mod-ified JESD204B interface is incorporated, focusing on simplified control and reduced implementation over-head. The system is described using Verilog HDL and simulated using FPGA design tools. The results confirm accurate analog-to-digital conversion along with im-proved data transmission efficiency and reduced power consumption. The proposed design is suitable for mod-ern communication and embedded applications.},
        keywords = {SAR ADC, RTL Modelling, Low Power Design, Simula-tion, Modified JESD204B Interface, High-Speed Data Conversion},
        month = {April},
        }