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@article{199914,
        author = {J. Sravanthi and P. Radhika and N. Pavankumar and M. Shiva Kumar and M. Shashi Reddy},
        title = {Design and Simulation of 8-bit Risc Processor using Verilog HDL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {12},
        pages = {253-257},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=199914},
        abstract = {-bit Reduced Instruction Set Computing (RISC) processor implemented using Verilog Hardware Description Language (HDL). The proposed processor adopts a Harvard architecture with separate instruction and data memories to enhance execution efficiency. A pipelined architecture is incorporated to improve overall system performance, enabling the execution of one instruction per clock cycle under ideal conditions. The processor consists of key functional units, including an arithmetic logic unit (ALU), register file, control unit, program counter, and memory modules. A simple yet efficient instruction set is designed to support fundamental arithmetic, logical, and data transfer operations. The design is described using Verilog HDL and simulated using industry-standard simulation tools to verify functional correctness.},
        keywords = {8-bit RISC Processor, Verilog HDL, Harvard Architecture, Pipelining, FPGA Implementation, Arithmetic Logic Unit (ALU), Instruction Set Architecture (ISA), Simulation.},
        month = {May},
        }