Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{177942,
        author = {J. SRAVANTHI and G. P. N. TEJASWI and K. BHANU PRASAD and K. SAGARIKA and K. MAHESH},
        title = {VLSI REALIZATION OF AREA-EFFICIENT CARRY SELECT ADDER},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {2099-2103},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=177942},
        abstract = {This paper presents an optimized approach to datapath logic design in VLSI systems by replacing Ripple Carry Adders (RCA) in Carry Select Adders (CSLA) with Binary to Excess-1 Converters (BEC). This substitution significantly enhances speed and reduces power usage and it also reduce the area, addressing key challenges in modern chip design. As VLSI continues to scale, managing power, delay, and area becomes critical. The proposed method supports compact, energy-efficient layouts suitable for high-speed digital systems. Implemented using CMOS technology and described in HDL, the design aligns with current trends in automated digital design, while supporting greater performance in embedded and applications.},
        keywords = {RCA, BEC, CSLA, etc…},
        month = {May},
        }