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@article{203634,
        author = {Gourish Guruprasad and C R Byrareddy},
        title = {Implementation of PMOS Biased Sense Amplifier},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {12},
        pages = {12658-12662},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=203634},
        abstract = {Sense amplifiers are critical components in SRAM memory systems that detect and amplify small voltage variations developed on memory bit-lines during read operations. The sense amplifier's stability, power consumption, and sensing speed all have a significant impact on SRAM performance. This study used 180 nm CMOS technology in the Cadence Virtuoso environment to develop and execute two PMOS-biased sense amplifier circuits. The suggested circuits' sensing delay, waveform stability, and regenerative behavior were assessed in both standalone and SRAM-connected scenarios. The practical performance of the suggested architectures was investigated through transient and post-layout simulations. For high-speed and low-power SRAM applications, the results show enhanced sensing operation, dependable output production, and decreased sensing delay.},
        keywords = {},
        month = {May},
        }