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@article{204317,
        author = {Goli Prema Harini and Kanteti Umasree and Majji Jyothi},
        title = {Design and FPGA Implementation of a Parameterized Synchronous FIFO Using Verilog HDL and TCL-Based Automation in Xilinx Vivado},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {1983-1990},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204317},
        abstract = {First-In First-Out (FIFO) memory structures play a vital role in modern digital systems by providing temporary data storage and synchronization between modules operating at different processing rates. This paper presents the design, implementation, and hardware validation of a parameterized synchronous FIFO using Verilog Hardware Description Language (HDL) on the EDGE Artix-7 FPGA development board. The proposed FIFO architecture supports configurable data width and memory depth, enabling scalability and flexibility for various FPGA-based applications. The FIFO design incorporates dedicated read and writes pointer management, full and empty status flag generation, and a Finite-State-Machine (FSM)-based debounce circuit for reliable push-button operation during hardware testing. The complete FPGA development workflow is automated using Tool Command Language (TCL) scripting in Xilinx Vivado, allowing project creation, source integration, synthesis, implementation, bitstream generation, report extraction, and FPGA programming through command-line execution. Functional verification is performed through simulation, while hardware validation is carried out using onboard switches, push buttons, and LEDs. Synthesis and implementation results demonstrate successful FIFO operation with efficient resource utilization and reliable data transfer.},
        keywords = {FIFO, FPGA, Verilog HDL, Xilinx Vivado, TCL Scripting, Artix-7, Synchronous FIFO, Hardware Automation, Digital Design, Memory Buffer.},
        month = {June},
        }