Design and Implementation of a Micro-Blaze Based Ethernet Lite Using FPGA IP Cores

  • Unique Paper ID: 204851
  • Volume: 13
  • Issue: 1
  • PageNo: 4161-4168
  • Abstract:
  • Design and implementation of a MicroBlaze-based Ethernet Lite communication system using FPGA IP cores on the Artix-7 Arty A7-35T platform. The proposed system integrates the MicroBlaze soft-core processor, AXI Ethernet Lite IP, AXI UART Lite, AXI Timer, AXI Interrupt Controller, and AXI Interconnect using Xilinx Vivado and Vitis tools. The lwIP lightweight TCP/IP stack is incorporated to support Ethernet communication and packet transmission between the FPGA board and host computer through static IP configuration. Experimental results confirm successful 10/100 Mbps Ethernet communication, ping response, TCP/IP packet transfer, and UART-based debugging. Comparative analysis with the existing Virtex-5 TEMAC-based system shows significant improvements in FPGA resource utilization, power efficiency, scalability, and debugging support. The proposed system achieved optimized FPGA resource utilization with 11,847 LUT usage and 22 BRAM utilization. The power consumption was also reduced from 12.27 W to 0.892 W, improving energy efficiency. The AXI-based architecture and Vivado/Vitis tool flow also improved system flexibility, reduced latency, and simplified hardware-software integration. The implemented system demonstrates a low-cost, lightweight, and efficient FPGA-based Ethernet communication solution suitable for embedded networking and industrial applications.

Copyright & License

Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{204851,
        author = {Suhas N D and Dr. Kalpana A B},
        title = {Design and Implementation of a Micro-Blaze Based Ethernet Lite Using FPGA IP Cores},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {4161-4168},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204851},
        abstract = {Design and implementation of a MicroBlaze-based Ethernet Lite communication system using FPGA IP cores on the Artix-7 Arty A7-35T platform. The proposed system integrates the MicroBlaze soft-core processor, AXI Ethernet Lite IP, AXI UART Lite, AXI Timer, AXI Interrupt Controller, and AXI Interconnect using Xilinx Vivado and Vitis tools. The lwIP lightweight TCP/IP stack is incorporated to support Ethernet communication and packet transmission between the FPGA board and host computer through static IP configuration. Experimental results confirm successful 10/100 Mbps Ethernet communication, ping response, TCP/IP packet transfer, and UART-based debugging. Comparative analysis with the existing Virtex-5 TEMAC-based system shows significant improvements in FPGA resource utilization, power efficiency, scalability, and debugging support. The proposed system achieved optimized FPGA resource utilization with 11,847 LUT usage and 22 BRAM utilization. The power consumption was also reduced from 12.27 W to 0.892 W, improving energy efficiency. The AXI-based architecture and Vivado/Vitis tool flow also improved system flexibility, reduced latency, and simplified hardware-software integration. The implemented system demonstrates a low-cost, lightweight, and efficient FPGA-based Ethernet communication solution suitable for embedded networking and industrial applications.},
        keywords = {vivado, Arty-A7, Microblaze, Ethernet lite},
        month = {June},
        }

Cite This Article

D, S. N., & B, D. K. A. (2026). Design and Implementation of a Micro-Blaze Based Ethernet Lite Using FPGA IP Cores. International Journal of Innovative Research in Technology (IJIRT), 13(1), 4161–4168.

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