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@article{207253,
        author = {Udaya Priya S and Poornima G},
        title = {Performance Enhancement of 6T SRAM Using Stacked SRAM Architecture},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {3},
        pages = {277-286},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=207253},
        abstract = {Static Random Access Memory (SRAM) is an important block of the VLSI system, widely used for caches in modern computers, in microprocessors, digital signal processors and for several embedded applications owing to their high speed and relatively low access time. However, advancement of continuous scaled CMOS technology aggravates the inherent problems of conventional 6T SRAM cell. These problems are higher leakage power, reduced SNM, poor standby power and read/write stability which limit the usage of 6T SRAM cell particularly in mobile application or portable device where power efficiency is essential.
This paper proposes the stacked 6T SRAM design that improve the performance of conventional 6T SRAM cells through usage of transistor stacking technique. In this work stack NMOS transistor are added in pull-down network to eliminate the sub-threshold leakage current by rising the effective threshold voltage and increasing the voltage across the OFF transistor. The proposed structure therefore results in low standby power. This architecture significantly improves the read and write stability and data retention. We have designed and simulate the proposed structure in CMOS technology and compared it with conventional 6T SRAM cell. We evaluated important parameter like average power, dynamic power, read/write delay and SNM of the cell for all operating points of temperature. Average power of conventional 6T SRAM cell reduces from 501.3mW to 71.3 mW with proposed stack SRAM design and similarly, average dynamic power from 408.8 mW to 52.9mW. The SNM of the conventional and the proposed 6T SRAM is achieved to 210mV and 315mV respectively, read delay is reduced to 0.47 ns and write delay is reduced to 0.52 ns.},
        keywords = {6T SRAM, Stacked SRAM, Leakage Reduction, Static Noise Margin (SNM), CMOS Technology, Low Power VLSI.},
        month = {August},
        }