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@article{210210,
        author = {Sarala B},
        title = {VLSI Implementation of a Chua Chaotic System-Based Secure Image Encryption Architecture},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {6},
        pages = {219-224},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=210210},
        abstract = {This paper presents a high-performance FPGA-based architecture for secure image encryption employing a chaos-driven cryptographic technique. Traditional image encryption approaches often encounter limitations, including restricted key space, vulnerability to statistical and differential attacks, and reduced processing efficiency for high-resolution images. To address these challenges, the proposed architecture integrates the nonlinear dynamics of Chua’s chaotic system with a hardware-efficient stream cipher to enhance encryption security and computational performance.Initially, chaotic sequences are generated using Chua’s circuit, numerically implemented through the fourth-order Runge–Kutta method with Q12.12 fixed-point precision. 
The resulting chaotic sequences are subsequently combined with a Linear Feedback Shift Register (LFSR) to produce pseudorandom keystreams suitable for efficient hardware realization. A reversible XOR-based diffusion mechanism is incorporated to strengthen the encryption process while ensuring lossless recovery of the original image during decryption.The proposed architecture employs a fully pipelined design capable of processing one pixel per clock cycle, making it suitable for real-time image encryption applications. The cryptographic strength of the system is assessed using statistical and differential security measures, including information entropy, adjacent-pixel correlation, Number of Pixels Change Rate (NPCR), and Unified Average Changing Intensity (UACI). Experimental observations indicate favorable entropy characteristics, minimal correlation between neighboring encrypted pixels, and strong differential sensitivity. Furthermore, the decryption process achieves exact reconstruction of the original image without pixel-level errors. These characteristics demonstrate the potential of the proposed FPGA architecture for secure, high-throughput image processing applications.},
        keywords = {Chaotic encryption, Chua’s circuit, RK4 solver, FPGA implementation, image security, LFSR},
        month = {November},
        }