32 bit ALU using Clock Gating and Carry Select Adder

32 bit ALU using Clock Gating and Carry Select Adder
Author(s):
Liril George, R.H. Khade, Padmaja Bangde
Keywords:
ALU, Clock Gating, FPGA, Spartan 3E, FPGA, CMOS, VHDL
Abstract
ALU is a fundamental building block of CPU found in computer. It does all process related to arithmetic and logic operations. As the operations become more complex,the ALU become more complex, more expensive and takes up more space in the CPU hence power consumption is a major issue.In this paper, a 32 bit ALU is designed using VHDL. Lower power consumption is achieved using clock gating and the results are compared with 32 bit ALU without clock gating. A carry select adder is used for the arithmetic unit to perform fast arithmetic functions.The design is then implemented in Xilinx Spartan 3E FPGA
Article Details
Unique Paper ID: 142364 Publication Volume & Issue: Volume 2, Issue 1 Page(s): 205 - 210
Article Preview & Download

Share This Article

NCSEM 2024

National Conference on Sustainable Engineering and Management - 2024

Last Date: 15th March 2024

IJIRT.org enables door in research by providing high quality research articles in open access market.

Send us any query related to your research on editor@ijirt.org