Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{145377,
        author = {Sundharamoorthy.s and Surendren.S and Sathishkumar.R and Riswan Mohamed.A},
        title = {A LOW POWER EFFICIENT N-MOS BASED 1-BIT FULL ADDER},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {9},
        pages = {450-454},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145377},
        abstract = {A Full adder is a basic and most important digital component. To improve the full adder architecture many improvements has been made. Nowadays efficient full adder circuit design is one of the main challenges for VLSI engineers.A full adder circuit is considered as one of the basic building blocks of Digital Signal Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated Circuits (ASICs) and many other digital circuits and systems.In recent times, various types of full adder circuits using different logic design styles have been proposed. In our work, a new NMOS based 1-bit full adder has been proposed which uses Pass Transistor Logic (PTL) technique in its design for improving performance. The result of the post layout simulation is implemented in TANNER TOOL.},
        keywords = {N-channel Metal Oxide Semiconductor (N-MOS); Full adder,Pass Transistor Logic (PTL), Power-Delay Product (PDP,Transistor (T).},
        month = {},
        }