Venkat Pedada, Namala Sreeja , Bheemaraju Jalandhar, Tulasi Naveen Kumar, K. Deepa Rao, D. Srikanth
VMM, Packets, Scoreboard, RTL etc.
This work presents the functional verification of logic modules for a Ethernet Switch for an ASIC based on the NetFPGA platform. A coverage-driven constrained random stimulus approach is used. It is implemented in a layered testbench environment with self-checking capability. This environment implements the methodology presented by the Verification Methodology Manual (VMM) using SystemVerilog. The main advantage of this methodology is its reusability. This characteristic enables the development of a common testbench environment for our modules with minimum changes for each particular module. The four logic modules presented in this work implement functions of a Ethernet switch. The common characteristic of these circuits is the close dependency between the time and its functionality. These modules need time information to deal with problems such as rate limiting, quality of service (QoS) or aging lookup tables in classification engines. As described in the literature, the transaction-level models used to predict the circuit behavior are time-independent when the implementation details are not relevant. But when time information influences the circuit functionality, the model needs to replicate the circuit latency to be functionally equivalent.We propose a simple solution to the synchronization process between the model and the design under verification (DUV). This solution preserves the main advantage of transaction-level models (faster simulation time than the RTL model) and generates the result data with the same circuit latency. These features made possible to run a considerable amount of test cases that helps to find and correct bugs in the circuit with a high confidence measured by the functional and code coverage results.
Article Details
Unique Paper ID: 155208

Publication Volume & Issue: Volume 9, Issue 1

Page(s): 137 - 140
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