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@article{161648,
        author = {Gomathi B and Divya K M and Amrine Fathima K and Abirami V S and Santhoshini P},
        title = {An Efficient Low Power Approach in Scaled VLSI Circuits using zero Heat Transfer},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {10},
        number = {5},
        pages = {278-284},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=161648},
        abstract = {Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL) approach is proposed as an efficient power reduction technique in this work to reduce the overall power consumption of any VLSI circuit. One of the most significant area of research in today’s VLSI domain is power reduction. By using a complementary phase-shifted voltage source, we can minimize the charging-discharging of the load capacitor in each clock pulse, which plays a vital role in reducing the circuits’ dynamic power consumption.1In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processors. To address this issue, a novel single-phase-clock dual-edge-triggering (DET) FF using a single-transistor-clocked (STC) buffer (STCB) is proposed. The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs.},
        keywords = {Adiabatic logic, low power, phase-shifted clock, two-phase clock, power clock generator.},
        month = {},
        }