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@article{143956,
        author = {Muthyla SukanyaRani and Atufa Rabia},
        title = {Recursive design of self-timed Brent Kung timer adder},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {3},
        number = {4},
        pages = {339-343},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=143956},
        abstract = {In IC design environment, the chip performance is influence by design environment, schematic and sizing parameter of the transistor. Therefore, this study is an attempt to investigate the performance of Recursive design of self-timed Brent Kung Parallel Prefix Adder.The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel.},
        keywords = {Brent Kung (BK) Adder, Ripple Carry Adder, Power, Delay},
        month = {},
        }