Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{144657,
        author = {B. NAGAMANI and D. MUTHILINGAM},
        title = {Novel Approach for implementation BISR (Built In Self Repair) With Redundancies in a System On-Chip For SRAMS},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {1},
        pages = {304-307},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=144657},
        abstract = {Therefore, we implemented an MBISR generator called BRAINS+, which automatically generates register transfer level MBISR circuits for SoC designers. The MBISR circuit is based on a redundancy analysis (RA) algorithm that enhances the essential spare pivoting algorithm, with a more flexible spare architecture, which can configure the same spare to a row, a column, or a rectangle to fit failure patterns more efficiently. The proposed MBISR circuit is small, and it supports at-speed test without timing-penalty during normal operation, e.g., with a typical 0.13μm complementary metal- oxide-semiconductor technology, it can run at 333 MHz for a 512 Kb memory with four spare elements (rows and/or columns), and the MBISR area overhead is only 0.36%. With its low area overhead and zero test-time penalty, the MBISR can easily be applied to multiple memories with a distributed RA scheme. Compared with recent studies, the proposed scheme is better in not only test-time but also area overhead. },
        keywords = {Redundancy Analysis, SoC, SRAM, MBISR.},
        month = {},
        }