Optimized Logic Synthesis of reversible PLA

  • Unique Paper ID: 144658
  • Volume: 4
  • Issue: 1
  • PageNo: 308-311
  • Abstract:
  • Reversible logic have been motivated by consideration of zero-energy computation. Reconfigurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA(Programmable Logic Array) with a newly designed low cost3 × 3 reversible NMG (New Mux Gate) circuit for Implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. In addition, we propose a heuristic to sort and to realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. The proposed Algorithms make the design efficient with improvement in number of gates, garbage count and quantum cost metric than existing technique save ragely. Performance is also analyzed by using MCNC benchmark circuits.. The proposed architecture of this paper analysis the logic size and area using Xilinx 14.3.
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Copyright © 2025 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

BibTeX

@article{144658,
        author = {k.Vamshi Krishna and Vasavi Sikilambatla },
        title = {Optimized  Logic  Synthesis of reversible PLA},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {1},
        pages = {308-311},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=144658},
        abstract = {Reversible logic have been motivated by consideration of zero-energy computation. Reconfigurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA(Programmable Logic Array) with a newly designed low cost3 × 3 reversible NMG (New Mux Gate) circuit for
Implementing multi-output ESOP (Exclusive-OR Sum of Product) functions. In addition, we propose a heuristic to sort and to realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. The proposed
Algorithms make the design efficient with improvement in number of gates, garbage count and quantum cost metric than existing technique save ragely. Performance is also analyzed by using MCNC benchmark circuits.. The proposed architecture of this paper analysis the logic size and area using Xilinx 14.3.
},
        keywords = {Reversible logic, Quantum Computing, PLA,non-reversible counterparts.},
        month = {},
        }

Cite This Article

  • ISSN: 2349-6002
  • Volume: 4
  • Issue: 1
  • PageNo: 308-311

Optimized Logic Synthesis of reversible PLA

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