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@article{160996,
        author = {P. Tamilmozhi and Dr.K.Somu and Mrs.M.Meena},
        title = {FPGA BASED PWM TECHNIQUES FOR CONTROLLING VOLTAGE SOURCE INVERTER},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {10},
        number = {2},
        pages = {278-283},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=160996},
        abstract = {A built-in self-repair analyzer with the best repair rate for redundant memory arrays is used in this project. The prevailing methods made use of a stack and a finite-state machine for depth first search. The circuit's design enables use of the parallel prefix method, and it may be set up in a variety of ways to satisfy space and test time needs. The number of content addressable memory entries used to hold the defect addresses makes up the majority of the infrastructure overall, and it only increases quadratically as the number of repair elements increases. In the BIST architecture, the linear feedback shift register is utilised to count the subsequent state and also necessitates high transitions. To locate the defect address to store in mustrepair analyzer, the content addressable memory is used. The suggested approaches make use of pre computation content addressable memory and bit swapping linear feedback shift registers to minimise transition and power consumption, respectively, as well as to shorten the time delay in the analyzer that needs repair. Even in the worst situation, only one test is needed. It selectively stores fault addresses by carrying out the must-repair analysis during the test, and uses the saved fault addresses for the final analysis to provide a solution. Additionally, the architecture has been expanded to accommodate several word-focused memory types.},
        keywords = {PWM, FPGA, ASIC, AISCPWM},
        month = {},
        }