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@article{176197,
        author = {Sanampudi Raviteja and S Madhava Rao},
        title = {ANALOG LAYOUT DESIGN OF ADC, DAC & PHYSICAL VERIFICATION},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {11},
        pages = {4988-4992},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=176197},
        abstract = {Analog Layout Design is a part of physical design in Analog design flow. In the fabrication process to perform lithography step masks are required to im- plant the desired pattern on the wafer and these masks are nothing but the layouts designed on layout editor. Normally after the circuits are designed and the outputs are verified after simulations, layouts have to be drawn for these circuits so that they can be fabricated. Layouts are nothing but geometrical representation of circuits using different layers and polygons. Layout design is a four-step process i.e. floor plan, placement, routing, and verification. Floor plan is an area estimate, placement is fixing the positions of devices or blocks, routing is the connections between devices or blocks and verification is done by DRC, LVS check. DRC checks whether the layouts designed are according to design rules provided by fabrication companies or not and LVS checks for connectivity, device properties, stamping conflicts, open or short circuits etc. Electro Migration checks whether the specified current is flowing through particular net or not and parasitic extraction is to make sure that the metal parasites are not degrading the circuit performance. Analog Layout design is complex job as there is no perfect automation and also analog circuits are so sensitive to temporal variations. The present work gives a clear idea about the Analog Layout Design and also the issues involved in Analog Layout Design.},
        keywords = {DRC, LVS},
        month = {April},
        }