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@article{178056,
        author = {SANAMPUDI RAVITEJA and S.MADHAVARAO},
        title = {DESIGN & ANALYSIS OF 32 BIT VEDIC MULTIPLIER USING PARALLEL PREFIX ADDER FOR LOW POWER APPLICATIONS},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {2305-2307},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=178056},
        abstract = {Multiplication plays a vital role in digital signal processing, image processing, and various computational tasks, where the efficiency of the multiplier directly influences overall system performance, particularly in low-power environments. This paper introduces a 32-bit Vedic multiplier architecture that incorporates a parallel prefix adder to enhance speed and minimize power consumption. Leveraging the principles of ancient Indian Vedic mathematics, the design enables efficient partial product generation and reduced computational complexity. The integration of a parallel prefix adder in the accumulation phase further accelerates computation and improves energy efficiency. Comprehensive analysis in terms of power, area, and delay confirms the proposed design's suitability for high-performance, low-power applications.},
        keywords = {Vedic Multiplier, Parallel prefix Adder},
        month = {May},
        }