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@article{177904,
        author = {Dr.A.VIKAS and P.ASHWINI and M.VENU and M.VAMSHI GOUD},
        title = {PHASE NOISE ANALYSIS OF SEPERATELY DRIVEN RING OSCILLATOR},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {11},
        number = {12},
        pages = {2693-2697},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=177904},
        abstract = {This is about the design and simulation of a 3-stage ring oscillator in Cadence Virtuoso at 180 nm technology. The emphasis is on phase noise analysis under different conditions such as temperature, noise figure, and operating frequency. The oscillator is very important in PLLs and data recovery in serial communication. It employs high-performance inverters in a feedback loop. Layout is generated after implementation with Assura, and more stages in increasing the number of stages decrease phase noise. Transient, DC, and phase noise analysis are performed to analyze frequency response and performance.},
        keywords = {SDRO, phase noise analysis, cadence virtuoso, inverter.},
        month = {May},
        }