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@article{193298,
author = {NELLUTLA HARINI and MEDARI DEVAVARAM and NIMMALA SRUJAN REDDY and PADAKANTI VIVEK VARDHAN and Dr. D RAMADEVI},
title = {Design and Implementation of BIST Architecture for low power VLSI Applications using Verilog(HDL)},
journal = {International Journal of Innovative Research in Technology},
year = {2026},
volume = {12},
number = {9},
pages = {4641-4646},
issn = {2349-6002},
url = {https://ijirt.org/article?manuscript=193298},
abstract = {As Integrated Circuit (IC) technology scales into the deep sub-micron regime, the complexity of Testing-on-Chip has escalated, making external testing increasingly expensive and inefficient. This paper presents the design and implementation of a Built-In Self-Test (BIST) architecture specifically optimized for low-power VLSI applications using Verilog Hardware Description Language (HDL).
The primary challenge addressed is the high switching activity during the testing phase, which often exceeds the power constraints of functional mode, risking permanent circuit damage. To mitigate this, we propose an enhanced Linear Feedback Shift Register (LFSR) design utilizing a modified clock-gating scheme and a T-flip-flop-based transition reduction technique. This approach significantly reduces the toggle rate of test patterns without compromising fault coverage. The architecture comprises a Test Pattern Generator (TPG), an Output Response Analyzer (ORA), and a BIST controller.
The design is simulated and synthesized using industry-standard tools (e.g., Xilinx Vivado or Cadence Genus). Experimental results demonstrate a reduction in dynamic power consumption by approximately 20-30% compared to conventional LFSR-based BIST, while maintaining high stuck-at fault detection. The modular nature of the Verilog implementation ensures scalability for complex System-on-Chip (SoC) environments.},
keywords = {Index Terms—VLSI, BIST, Low Power, Verilog HDL, LFSR, Test Pattern Generation, Fault Coverage, SoC Testing.},
month = {February},
}
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