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@article{203062,
        author = {Akshaya M and Dorothy P and Gokul M},
        title = {DESIGN AND ANALYSIS OF AN OPTIMIZED 8T SRAM CELL},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {12},
        number = {12},
        pages = {10432-10440},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=203062},
        abstract = {Static Random Access Memory (SRAM) serves as a key component in modern electronic systems, especially within a processors operating at high frequencies, cache memory structures, and energy efficient embedded systems. With the continuous scaling of CMOS technology towards nanoscale dimensions, traditional SRAM structures face multiple design constraints [1], including higher leakage current effects, lower operating voltage levels, reduction in noise tolerance, and instability during read access. The commonly implemented 6T SRAM cell[4], while efficient, exhibits stability constraints because of shared access path used for both reading and writing processes, especially in deep sub-micron technologies.This paper describes the design and performance analysis of an 8-Transistor (8T) SRAM cell developed with 45 nm CMOS technology using the Cadence Virtuoso simulation platform[1]. The proposed 8T architecture introduces an imdependent read path that separates the internal storage nodes from the bit lines while reading data,which improves read stability and reducing read interference effects[6]. The circuit performance is evaluated through transient analysis, focusing on key parameters including power dissipation, signal delay, and stability during read operation[6].In addition, a comprehensive parametric analysis is conducted to examine the performance of the SRAM cell across different operating conditions. The simulation outcomes demonstrate that the proposed 8T SRAM cell achieves lower power usage, enhanced Static Noise Margin (SNM), and better operational reliability when compared to conventional 6T SRAM designs. These features make the 8T SRAM cell suitable for energy-efficient and high-performance VLSI systems, including portable devices, Internet of Things (IoT) systems, and advanced computing platforms.},
        keywords = {SRAM, 8T SRAM Cell, 45nm CMOS Technology, Low Power VLSI, Static Noise Margin (SNM), Read Stability, Leakage Power Reduction, Cadence Virtuoso, Transient Analysis, Parametric Analysis, CMOS Scaling, Memory Design, High-Speed Cache Memory, Embedded Systems},
        month = {May},
        }