Copyright © 2026 Authors retain the copyright of this article. This article is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

@article{204751,
        author = {Santhosh N and Gahan A V},
        title = {Design and Implementation of BIST Architecture for low power VLSI Applications using Verilog},
        journal = {International Journal of Innovative Research in Technology},
        year = {2026},
        volume = {13},
        number = {1},
        pages = {4752-4758},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=204751},
        abstract = {Modern VLSI systems contain highly complex logic and memory components, making fault detection using traditional external testing methods difficult, expensive, and time-consuming. This paper presents the design and implementation of a low-power Built-In Self-Test (BIST) architecture for a RISC-V processor using Verilog HDL. The proposed architecture integrates scan chain, Logic Built-In Self-Test (LBIST), and Memory Built-In Self-Test (MBIST) techniques to improve testability and fault coverage. The scan chain enhances controllability and observability of internal registers, while LBIST uses LFSR and MISR structures for automatic logic fault detection. MBIST employs a March-based algorithm to detect memory faults efficiently. The proposed system enables automatic PASS/FAIL generation without external testing equipment. Experimental results show improved reliability, reduced testing cost, faster fault detection, and optimized power, area, and delay performance for low-power VLSI applications.},
        keywords = {BIST, LBIST, MBIST, RISC-V Processor, Scan Chain, DFT, Verilog HDL, LFSR, MISR, Fault Detection, Low Power VLSI, Embedded Systems, Memory Testing, Logic Testing.},
        month = {June},
        }