FPGA Implementation of Efficient Advance Encryption Standard (AES) for High Power Drive Applications
K.S. Kavin, P. Subha Karuvelam, P. Kavitha, P. Malathi
AES, System Generator, FPGA, reconfigurable computing, HLL
The paper presents an efficient reconfigurable hardware implementation of Advance Encryption Standard (AES) algorithm on Field Programmable Gate Array (FPGA); using High Level Language (HLL) approach with less hardware resources. The FPGA platform used for AES implementation is Xilinx Atlys Virtex-6. Time-to-market is one of the key factors for any design in FPGA and digital system designing industry. This time can be reduced considerably with HLL approach. The presented algorithm is designed on a HLL tool, namely Xilinx system generator. It is very user friendly despite giving detailed control in designing the required system design. For actual testing and hardware implementation of the algorithm, the HLL-tool generates a bit file that can be directly burnt on the FPGA. To get the implementation of design on hardware, the presented work uses a similar approach to directly map the System Generator described design on FPGA. The presented work emphasizes on optimization for less hardware utilization. The presented design uses approximately just one thousand slices and about half a century of BRAMs.
Article Details
Unique Paper ID: 157535

Publication Volume & Issue: Volume 9, Issue 7

Page(s): 542 - 547
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