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@article{143957,
        author = {Kothakonda Lavanya and Keerthi Srilekha},
        title = {Design of Efficient Compressor & Adder Based MAC Architecture for DSP Applications},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {3},
        number = {4},
        pages = {344-349},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=143957},
        abstract = {DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power.},
        keywords = {Multiply Accumulate, Compressor, DSP, Adders, Low Power VLSI, Data path.},
        month = {},
        }