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@article{145073,
        author = {Mallikarjunarao Jangam and B.Ramarao},
        title = {Cadence Design of Transient Fault Tolerant Latches in 45nm Technology},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {4},
        number = {7},
        pages = {203-209},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=145073},
        abstract = {As the technology is going on increasing rapidly the electronic component units are also increasing. chip density is rapidly growing so there is a need for the low power  memory devices to transfer information from one place to another without any loss  so there is a need for building low power block of the memory device. so with the help of this block we can build efficient low power memory devices. A Transient Fault Tolerant latch  is presented that is insensitive to transient faults affecting its internal and output nodes by design, independent of the size of its transistors. The above Latch is implemented with 90nm and 45nm CMOS Technology and a comparative statement to be made for speed and power consumption. A novel 8-T Transient Fault Tolerant latch is proposed and the same is implemented with a standard 45 nm CMOS technology using Cadence tool. The proposed latch is going to be designed by changing the (W/L) ratios of the transistors to achieve low power. Our approach is to change the technology for obtaining better performance and low power compared to the previous approach. Our proposed latches are particularly suitable to be adopted on critical paths.},
        keywords = {Transient faults, soft errors, static latch, robust design},
        month = {},
        }