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@article{155226,
        author = {Naresh Boini and Parigi Sai Chandana and Dr.Md.Salauddin},
        title = {RAM Enabled Built in Self Test (BIST) for VLSI Circuits using Verilog},
        journal = {International Journal of Innovative Research in Technology},
        year = {},
        volume = {9},
        number = {1},
        pages = {309-312},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=155226},
        abstract = {Because of the fast size of combination in Integrated circuit plans which has reached submicron innovations, testing has developed to be a basic variable. Configuration engineers who don't plan frameworks in light of full testability open themselves to the expanded chance of item disappointments and botched market open doors. In such a situation where ordinary testing approaches are frequently ineffectual and lacking, BIST has demonstrated its worth. BIST is a plan method that permits a circuit to test itself. In this task the test execution accomplished with the execution of BIST is demonstrated to be sufficient to balance the disincentive of the equipment upward created by the extra BIST hardware. The strategy can give more limited test time contrasted with a remotely applied test and permits the utilization of minimal expense test hardware during all phases of creation. The idea was planned and executed with Xilinx ISE 14.2.},
        keywords = {LFSR, MISR, BIST controller},
        month = {},
        }