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@article{184982,
        author = {Mr. Tanay.M. Kherde and Dr. J. R. Shinde and Mr. Ganesh G. Patil},
        title = {Digital Clock with Stopwatch Functionality},
        journal = {International Journal of Innovative Research in Technology},
        year = {2025},
        volume = {12},
        number = {4},
        pages = {3969-3975},
        issn = {2349-6002},
        url = {https://ijirt.org/article?manuscript=184982},
        abstract = {This paper presents the design, simulation, and FPGA implementation of a digital clock integrated with a stopwatch functionality. The system is developed using Verilog HDL and verified through behavioral simulation in Xilinx Vivado. The digital clock accurately tracks hours, minutes, and seconds in a 24-hour format, while the stopwatch can be started, stopped, and reset using control inputs. The work focuses on hardware-level design optimization for FPGA devices, considering both area efficiency and timing performance. After simulation, the design is synthesized and implemented on a target FPGA board, where resource utilization, timing summary, and power analysis are performed. The proposed system demonstrates robust and reliable operation, with zero setup and hold violations, low power consumption, and minimal resource usage. The modular design approach ensures scalability, enabling future extensions such as multi- stopwatch support, alarms, high-precision timing, and display interfaces. This paper highlights how FPGA- based solutions can provide low-cost, reconfigurable, and educational-friendly timekeeping systems, suitable for real-time embedded applications.},
        keywords = {Digital Clock, Stopwatch, FPGA, Verilog HDL, RTL Design, Simulation, Synthesis, Timing Analysis, Xilinx Vivado, Low-Power Design, Real-Time Embedded Systems},
        month = {September},
        }