Design & Analysis of Power Efficient Flip Flop and its Application in Nanometer Technology

Santhoshini P; Yuvanesh Hari.M; Yugendran.S; Ajay Krishnan.M; D.S.Yashvaanth

Design & Analysis of Power Efficient Flip Flop and its Application in Nanometer Technology

Authors: Santhoshini P, Yuvanesh Hari.M, Yugendran.S, Ajay Krishnan.M, D.S.Yashvaanth

Unique Paper ID: 170937
Volume: 11
Issue: 7
PageNo: 2210-2214

Keywords: Switching power CMOS power consumption delay flip-flops

Abstract:
Due to continuous scaling of transistors and increasing requirement of portable equipment, power reduction is of main concern. For design of sequential circuits. flip-flops play very important role. Various existing single edge triggered master slave flip flops and pulse triggered flip flops are examined, simulated, analyzed and optimized in SPICE EDA tool. A novel design will be proposed that consumes low power when compared with the existing literature. The design shall not be only power efficient but area and delay constraints will also to be taken into consideration. The competitiveness of the new design (proposed work) will be shown in terms of power, area and delay with a comparison with existing design. Simulations will also be carried out at different voltage levels to check the viability of the design. Not only voltages, calculations at various data activity (duty cycle) will be obtained for fair comparison and optimum power saving. The proposed work is desired to find application in sequential circuits.

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Cite This Article

ISSN: 2349-6002
Volume: 11
Issue: 7
PageNo: 2210-2214

Design & Analysis of Power Efficient Flip Flop and its Application in Nanometer Technology

Available:https://ijirt.org/Article?manuscript=170937

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